1. Field of the Invention
This invention relates to electronics, and more particularly, to a current-switching method and circuit for digital-to-analog converters (DACs) with improved compliance and linearity in the output current.
2. Description of Related Art
Most conventional DACs are constructed based on a current-switching architecture. Earlier current-switching circuits are designed to operate at 5 V (i.e., the high-voltage logic state of the digital input is 5 V). However, today's digital systems are typically designed to operate at 3.3 V or 3 V. Therefore, when a conventional 5 V current-switching circuit is used on a 3 V digital system, it would not meet the required 1.2 V compliance and high linearity in the output current characteristic. Two such conventional current-switching circuits are illustratively depicted in the following with reference to FIGS. 1 and 2 respectively.
FIG. 1 is a schematic circuit diagram of a first conventional current-switching circuit for DAC. As shown, this current-switching circuit is composed of three MOS transistors M1, M2, M3. The first MOS transistor M1 serves as a fixed current source. The second MOS transistor M2 has a gate G2 connected to receive a first digital input DIN, while the third MOS transistor M3 has a gate G3 connected to receive a second digital input DINB. Whether the output port T.sub.IOUT of the current-switching circuit outputs current or not is dependent on the logic combination of the first and second digital inputs DIN, DINB, This current-switching circuit can operate at 3 V (V.sub.CC =3V) and therefore can be used in conjunction with a 3 V digital system.
One drawback to the foregoing current-switching circuit, however, is that during the switching of the first and second digital inputs DIN, DINB from one logic sate to the other (either from low to high or from high to low), there exists a short period in which both of the two MOS transistors M2, M3 are switched simultaneously to the OFF state, thus leading to the undesired occurrence of a current spike in the output current IOUT. One solution to this problem is to incorporate buffer means (not shown) to the current-switching circuit. To do this, however, the overall chip size to implement the current-switching circuit will be increased.
Still one drawback to the foregoing current-switching circuit is that the linearity in the output current characteristic is poor due to the reason that MOS transistor M3, which operates in the triode region, is used at the output port of the current-switching circuit to provide the 1.2 V output compliance, which is insufficient to provide a high enough output impedance at the output port of the current-switching circuit. Therefore, the linearity in the output current characteristic is still unsatisfactory.
Another solution to the problem of the simultaneous switching-off of the two MOS transistors M2, M3 in the circuit of FIG. 1 is shown in FIG. 2. The current-switching circuit of FIG. 2 is substantially identical in circuit structure as the one shown in FIG. 1, except that the input to the gate G3 of the third MOS transistor M3 is here a fixed reference voltage VREF instead of the digital input DINB. This modification can help prevent the two MOS transistors M2, M3 from being simultaneously switched to the OFF state. However, the linearity in the output current characteristic is nonetheless unsatisfactory.